CS4360-KZZ【PDF 9/37 页】IC DAC STER 6CH 102DB 28TSSOP

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Sheet目录1991

5页 6页 7页 8页 [9页]10页 11页 12页 13页

CS4360

DS517F2

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE

Inputs: Logic 0 = GND, Logic 1 = VLC

Notes: 7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

8. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

for Single-Speed Mode,

for Double-Speed Mode,

for Quad-Speed Mode.

Parameter

Symbol

Min

Max

Unit

IC Mode

SCL Clock Frequency

fscl

100

kHz

RST Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

Clock Low time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 7)

thdd

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL and SDA

trc, trc

-1

Fall Time SCL and SDA

tfc, tfc

300

Setup Time for Stop Condition

tsusp

4.7

Acknowledge Delay from SCL Falling

(Note 8)

tack

(Note 9)

256

---------------------

128

---------------------

64Fs

------------------

buf

hds t

lo w

hd d

high

su d

Sto p

S t a r t

SD A

SC L

irs

RS T

hdst

t sust

t susp

St a r t

Sto p

R e pe at e d

ac k

Figure 13. Control Port Timing - IC Mode

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